Supply Voltage Scalable System Design Using Self-Timed Circuits

Supply voltage scalable system design for low power is investigated using self-timed circuits in this paper. Two architectures are proposed to achieve supply voltage scalability, for preserved quality and energy-quality tradeoff respectively, In the fist architecture, the supplyvoltage automatically tracks the input data rate of the data path so that the supply-voltage can be kept as small as possible while maintaining the speed requirement and processing quality. In the second one, further energy saving is achieved at the cost of signal-noise-ratio loss in digital signal processing when an ultra-low supply voltage is applied. Cadence simulation shows the effectiveness for both architectures. More than 40% to 70% power can be saved by introducing -15dB to -10 dB error in a case study: speech signal processing.